The invention relates- generally to a pipelined charge-to-digital converter (CDC), and more particularly to a charge coupled device (CCD) charge-to-digital converter used to compute the digital representation of an input charge quantity.
Charge coupled devices are well known monolithic semiconductor devices and are widely used in applications such as visible and infrared imaging, analog delay lines, analog filters, and high speed analog memories. In most applications, a digital representation of the analog charge signal is ultimately desired. Digitizing charge quanta is traditionally performed by an indirect procedure. First, the charge quantity is converted to an analog voltage which is buffered and driven off-chip. External correlated-double-sampling circuitry is then used to reduce the effect of nonidealities introduced by the charge-to-voltage conversion. Finally, the signal is sampled by a sample-and-hold and the result is digitized by a conventional A/D converter. This entire process must be extremely low-noise, requires significant hardware and power, is not readily extendible to higher speeds, and can not easily be integrated onto a focal plane.
There are two fundamental drawbacks with the traditional approach. First, the input signal which is in the form of a charge quantity is converted to a voltage. Second, the discrete-time input signal is converted to continuous-time signal, which then must be resampled. Both of these operations are eliminated by computing the digital representation of the charge signal on chip in the charge domain. In this way, the charge-to-voltage translation, correlated-double-sampling, analog amplifiers, sample-and-hold, and external A/D converter are all eliminated and the entire path is replaced by a single charge-to-digital converter.
Conventional charge-to-digital converters are disclosed in the following U.S. patents, the disclosures of which are incorporated herein by reference: U.S. Pat. Nos. 4,489,309 (Schlig), 4,375,059 (Schlig), 4,171,521 (Wang et al.), 5,189,423 (Linnenbrink et al.), 5,061,927 (Linnenbrink et al.), 4,471,341 (Sauer), 4,329,679 (Jensen), 3,806,772 (Early), 5,014,059 (Seckora), 4,326,192 (Merrill et al.), and 4,107,550 (Jacquart et al.). Many of the prior art systems are subject to severe accuracy limitations. These systems either require operations, such as subtraction, which can not easily or accurately be performed using CCDs, or they contain a single-ended signal flow. Schlig '309 discloses a significantly improved charge-to-digital converter. It has a fully differential architecture, requires only the operations of addition and division by two, and can be easily and accurately implemented using CCD technology.
The resolution (the size of a quantization step) of the converter described in Schlig '309 is unfortunately restricted by the maximum achievable sensitivity of charge-to-voltage conversion using conventional floating-gate means and by the minimum achievable voltage resolution of a comparator. A floating-gate means of charge sensing always results in a gain of less than unity. In other words, the gate's resulting voltage swing is less than the channel potential modulation caused by an input charge. The maximum allowable output voltage using this technique is determined by the technology and the clocking method used and is typically limited to a small fraction of the full power supply range. In this case, an increase in the charge resolution corresponds to a smaller LSB voltage swing and necessarily requires a corresponding increase in the resolution of the comparators.
The dynamic range (the number of quantization levels) of the Schlig '309 converter is also constrained by the maximum allowable input common-mode range of the comparators and by mismatches between different sensing paths. The device accomplishes subtraction by performing addition to a complimentary signal and, therefore, accumulates a large common-mode signal along the pipeline. Within each stage, two charge quantities are independently converted to voltages and then differentially compared. Mismatches between different sensing paths, amplified by the common-mode signal, must remain less than the differential signal corresponding to an LSB. A more sensitive method of charge-to-voltage translation than a conventional floating-gate technique is desirable for resolving small differential signals. However, this can not be achieved using the prior art converter because translation of the common-mode signal must remain within the allowable input range of the comparators.
It is therefore an object of the present invention to provide a charge-to-digital converter with improved charge resolution by amplifying signals in the charge-domain prior to charge-to-voltage conversion and comparison.
It is a further object 0f the present invention to provide a charge-to-digital converter with increased dynamic range, and reduced sensitivity to systematic mismatches by suppressing common-mode signals in the charge-domain before charge-to-voltage conversion.
It is a still further object of the present invention to provide a charge-to-digital converter with reduced susceptibility to dynamic sensing noise and to sensing mismatches by sensing signals multiple times over multiple stages.
It is another object of the present invention to provide a charge-to-digital converter with reduced power consumption and reduced comparator requirements by performing all critical processing on signals in the charge-domain.
It is yet another object of the present invention to provide a charge-to-digital converter with reduced susceptibility to comparator errors by incorporating digital error correction techniques.